Carrier phase detectors are conventionally subdivided into two different groups, specifically into the group of so-called DD carrier phase detectors, and into the group of so-called NDA carrier phase detectors. During the synchronization of the receiver with the carrier signal, the carrier phase and the carrier frequency of the modulated received signal are not known in advance. The phase error of the received signal from a desired nominal phase is calculated for carrier synchronization using the carrier phase detector by means of a carrier phase loop, which forms a control loop.
The received signal comprises a sequence of received data symbols, with each data symbol comprising, for example, 2 bits. In this case, the first bit indicates the real part of the transmitted data symbol, and the second bit indicates its imaginary part. The carrier phase detector calculates a feedback signal for the carrier phase loop within the receiver as a function of the real part and the imaginary part. The feedback signal is filtered by a downstream loop filter.
FIG. 1 shows the calculated feedback signal of a DD carrier phase detector based on the prior art on the complex plane, with the x axis representing the real part of the received data symbol, and the y axis representing the imaginary part of the received data symbol. The DD carrier phase detector according to the prior art weights the input data symbols linearly:D=−Re Sign(Im)+Im·Sign(Re)  (1)
The darker the shading in FIG. 1, the more negative is the value of the feedback signal D emitted from the DD carrier phase detector.
By way of example, the following table is obtained for the following four received data symbols Ei:
TABLE 1E1E2E3E4Re11.10.11.9Im10.91.90.1D0−0.2+1.8−1.8
If the received data symbol is located in the upper left-hand corner of the first quadrant on the complex plane (for example E3=(0.1; 1.9), the value of the emitted feedback signal D has a high positive value (for example D3=+1.8).
If the received data symbol is in the right-hand lower corner of the first quadrant of the complex plane (for example E4=(1.9; 0.1), a high negative value is emitted as the feedback signal from the carrier phase detector (D4=−1.8).
In the case of a 4 PSK-modulated signal, four equidistant nominal data symbols are defined, for example:Enom1=(+1; +1);Enom2=(−1; +1);Enom3=(−1; −1) ;Enom4=(+1; −1)
In this case, the four (m=4) different nominal data symbols Enom are located in the four different quadrants (I-IV) of the complex plane, as is illustrated in FIG. 1.
The nominal phase in the example illustrated in FIG. 1 is Enom=45° for the four nominal data symbols.
The DD carrier phase detector calculates the feedback signal D for each received data symbol which has a nominal phase of φ=45° to be D=0.
One disadvantage of DD detectors according to the prior art, which calculate the feedback signal D in accordance with equation (1), is that there is a hard transition between the individual decisions. A bright region with a high positive feedback signal value and a dark region with a relatively high negative feedback signal value D are located directly alongside one another, and can be seen from FIG. 1. In the case of a high positive feedback signal value D of, for example, +1.8, the carrier phase loop rotates in the clockwise direction, while the carrier phase loop rotates in the anticlockwise direction when the feedback signal has a high negative value of, for example, D=−1.8.
In the DD carrier phase detector according to the prior art as shown in FIG. 1, those received data symbols which are located at the boundary between the phases of two nominal data symbols are weighted more heavily than received data symbols which are located in the vicinity of the nominal phase of φ=45°. The received data symbols E3, E4, which have a relative high phase error with respect to the nominal received data symbol Enom1=(1; 1) thus lead, for example, to a feedback signal D with a large amplitude, specifically of D3=+1.8 and D4=−1.8. In contrast, a received data symbol which has a relatively small phase error with respect to the nominal data symbol (Enom=(1.1)), specifically the received data symbol E2=(1.1; 0.9), leads to a feedback signal value of D=−0.2, that is to say the amplitude of a received data symbol which has a smaller phase error with respect to the nominal received data symbol is less than the amplitude of the feedback signal D for a received data symbol which has a relatively large phase error from the nominal data symbol. Now, however, those particular received data symbols which have a relatively large phase error with respect to a nominal data symbol are relatively inaccurate. For example, a received data symbol E=(1, 0) has the same phase error with respect to the nominal data symbol in the first quadrant (Enom=(1.1)) and with respect to the nominal data symbol in the fourth quadrant (Enom4=(1, −1)). The probability that a received data symbol Enom which is located precisely on the boundary will correspond to the first nominal data symbol Enom1 or the fourth received data symbol is 50%. The DD phase carrier detector according to the prior art and as shown in FIG. 1 thus does not take account of the reliability probability of the received data symbol, and, accordingly, the variance of the signal amplitudes of the feedback signal D which is calculated by the DD carrier phase detector according to the prior art is relatively high. Accordingly, the power gain of the downstream digital loop filter should be designed to be less, so that the stabilization times of a carrier phase loop which uses a DD carrier phase detector according to the prior art as shown in FIG. 1 are relatively high. Thus, if the received signal changes quickly, the receiver is not able to follow the signal quickly, so that the bit error rate rises.
FIG. 2 shows a feedback signal D on the complex plane, which is calculated by means of an NDA carrier phase detector according to the prior art. An NDA carrier phase detector such as this is described, for example, by A. J. Viterbi and A. M. Viterbi “non linear estimation of PSK-modulated carrier phase with application to burst digital transmission” in IEEE TransInfoTheory volume IT-32, pages 543-551 (July 1983). The feedback signal D for Q PSK and 4 PSK is calculated using the following equation:
  D  =                                          r            x                    ·          Mod                ⁢                                                                      Arg                ⁡                                  (                                                            (                                              Re                        +                                                  j                          ·                          Im                                                                    )                                        4                                    )                                            +                              2                ⁢                π                                      ,                          2              ⁢              π                                                    -      π        2  where, in principle, x is freely variable, but x is normally set to be equal to zero, so thatr=√{square root over (Re2+Im2)}=1  (3)
In the case of an NDA carrier phase detector such as this, the following values are obtained for the digital feedback signal D for four examples of received data symbols E1-E4:
TABLE 2E1E2E3E4Re11.10.11.9Im10.91.90.1D0−0.199+1.466−1.466
The NDA carrier phase detector according to the prior art and as shown in FIG. 2 in fact has the same disadvantage as that of the conventional DD detector according to the prior art as shown in FIG. 1 in that there is a hard transition between the individual decisions.
Owing to the high signal variance of the calculated feedback signal D, the stabilization response for a carrier phase loop which has an NDA carrier phase detector such as this is relatively poor. This means that the carrier phase loop stabilizes only slowly, since the loop gain of the downstream digital loop filter must be set to be relatively low.